The VHDL JPEG encoder core implements a high-performance image encoder that complies with the baseline ISO/IEC 10918-1 JPEG standard. The core throughput range is 100 to 266 Mbyte/sec working in FPGA on clock 100MHz.

The compression speed depends on the image quality (quantization coefficients)

The technical specifications and advantages using the FPGA code for JPEG are as follows:

• Encodes over 88 frames/sec for4:3 HDTV, 1440x1152, 4:2:0 or over 70 frames/sec for 16:9 full HDTV, 1920x1080, 4:2:0.

• Image compression speed for different subsampling (core clock = 100 MHz): YUV 444 - 33 to 88 Mpixels/sec -(typical 77 Mpixels/sec) YUV 422 (horizontal or vertical) - 50 to 133 Mpixels/sec - (typical 116 Mpixels/sec) YUV 420 - 66 to 176 Mpixels/sec - (typical 155 Mpixels/sec) Grayscale - 100 to 266 Mpixels/sec - (typical 230 Mpixels/sec)

• Any image size up to 64k x 64k is supported by the core.

• Programmable Huffman tables (DC, AC) and quantization tables (luminance, chrominance) are supported.

• Supports separate clock speed for interface modules and engine modules.

• Additional SRAM controller automatically reads input block (8x8 pixels) from SRAM memory according to subsampling